Connectors pinout: Difference between revisions
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1:8 [[Logic Analyser]]<7:0> | 1:8 [[Logic Analyser]]<7:0> | ||
9 External Trigger | 9 External Trigger (Input) | ||
10 GND | 10 GND | ||
11 [[Arbitrary_Waveform_Generator_(AWG)|AWG Output]] | 11 [[Arbitrary_Waveform_Generator_(AWG)|AWG Output]] | ||
Revision as of 21:11, 28 September 2015
Available in excel format
J12 - AUX
1 8
_____________________________________
| _______--________ |
| | . . . . . . . . | |
| -- === | . . . . . . . . | |
| `-----------------' |
`-------------------------------------'
9 16
1:8 Logic Analyser<7:0> 9 External Trigger (Input) 10 GND 11 AWG Output 12 GND 13:16 Digital out <0:3>
J8 - FPGA to PIC
,-----------. ,-------------. 8 | P71 | GND | 7 8 | DONE | GND | 7 |-----+-----| |------+------| | P39 | P70 | | DIN | CCLK | |-----+-----| |------+------| | P65 | P32 | | D7 | D6 | |-----+-----| |------+------| | P27 | P29 | | D5 | D4 | |-----+-----| |------+------| | P22 | P26 | | D3 | D2 | |-----+-----| |------+------| | P15 | P21 | | D1 | D0 | |-----+-----| |------+------| 14 | NC | GND | 1 14 | NC | GND | 1 `-----------' `-------------'
J9 - Bottom left
8 5 8 5 ,-----------------------. ,-----------------------------------. | 3V3 | P57 | P62 | P58 | | 3V3 | OPAB | B_MUL_1 | B_MUL_2 | |-----+-----+-----+-----| |-----+---------+---------+---------| | GND | P78 | P104| P84 | | GND | GPIO2 | GPIO5 | GPIO4 | `-----------------------' `-----------------------------------' 1 4 1 4
J10 - Top left
8 5 8 5 ,-----------------------. ,----------------------------------------. | 3V3 | 5V | P74 | P59 | | 3V3 | 5V | GPIO3 | GPIO1 | |-----+-----+-----+-----| |-----+--------------+---------+---------| | GND | P56 | P66 | P69 | | GND | A_DIV_10_100 | A_MUL_2 | A_MUL_1 | `-----------------------' `----------------------------------------' 1 4 1 4